Saturday, September 4, 2010

cisco interview questions

Here are some CISCO Interview Questions consisting more of Digital Electronics written and technical interview Questions asked in leading electronics companies / software development or chip designing firms.
Why do we use refresh in dynamic RAM?
Explain the cause and effect signals of 8085 microprocessor.
What is FILO?
Why is CMOS preferred over NMOS?
What happens if we add negative logic to a nand gate?
Difference between synchronous circuits and asynchronous circuits.
What do you know about ALE in 8085?
ALE stands for Address latch enable.
Bit storage capacity of a ROm with 512*4 organization?
What is the time taken by a 64 kbps serial link to send a picture with 540 pixels?
How much memory is required to store a 4 minutes voice signal. Frequency range = 16 to 20 Hz and sample = 1 byte.
Explain Subroutine and Vectored Interrupts.
Memory needed for multiplication of two 8 bit unsigned numbers.
How does a controller work?
What is the vector address of RST 7.5 in 8085 microprocessor?
Represent AC2H in terms of Gray code
Active high SR latch has 1 on S and 0 on R input. What is the state of latch?
What is a PLL?
What are the various stages inside a PLL or phase locked loop?
The input of a D flip flop is connect to output of an XOR gate, What will be the output?
How does the Icb of a transistor vary with change in temperature?
How many input vectors are required to determine the stack fault of a 3 input nand gate?
What is the range of mantissa in a normalized floating point representation?
Question on Addition of BCD Numbers
Question on Addition of Hexa decimal Numbers
Subtraction of hexa decimal numbers
Simplification of complex expressions
How is nor gate used as an inverter?
What is the number of flip flops needed to make a divide by 32 device?
What do you understand by a parity generator?
Digital Electronics important technical interview and written test paper theoretical questions and answers. Download lots more related tech and job preparation materials here.
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Quick Thinking Tests

  • 200lb of cucumbers was delivered to the grocery store and left in a storage room. The cucumbers contained 99% of water. After some time part of water evaporated and the contents of water in cucumbers became 98%. What is the weight of cucumbers now?






  • You have 2 candles. Every candle lights for 60 minutes. You have to find the way to measure  45 minutes.





  • A snail wants to creep on to the top of the tree 5m high. During the day it can creep up 3m but during the night it creeps down 2m. How many days does it need to reach the top?





  • 9 coins,one of them is fake. Use a balance to weigh them not more than 3 times and find the fake.A fake coin is not necessarily lighter.





  • Connect  9 dots with 4 lines . Don't cross the same dot twice.
    • .             .            .   .             .            .   .             .            .
  • Parachutist is landing the island  in the darkness. The island is of unknown shape. There must be a fenced lot at the island. The parachutist needs to find out if he is within the fenced lot or outside.
  • A band is going in the street with a constant speed.Someone in the last raw has a dog.The dog runs ahead, reaches the front line of the band and gets back to it's owner. The dog's speed was also constant all the way and while it was running the band passed 50 feet. Find the length of the dog's path,if the distance between the front and the rear line of the band is 50 feet.

  • There are 100 gold coins in 10 columns by 10 coins in each column. Every coin weights 1 lb. One column contains 10 fake coins.Each coin in it weights 0.9 lb. Take one measurement to find the column with fakes.
    Sent Hari R., National Semiconductor

  • Two drivers are going to the next town which is 100 miles away. They depart at the same time, however the first driver stops for gas during the first 50 miles, the second driver stops during the second half. Each stop takes 10 minutes. They both drive with the same speed 60 mph during the first 50 miles and 65 mph during the second half. Who, do you think, arrives first?

  • A chess board has 64 squares.Two squares in the diagonal corners are masked out.Is it possible to cover the rest 62 squares with 31 dominos? (One domino covers two squares.) Explain the logic of your answer.



  • There are four numbers: 1, 2, 5, 10 that you have to carry in a boat across a river. Every time you may not carry more than two numbers , and the time of traveling is associated with the largest of two numbers. One number has to be in the boat during the return journey, which also defines the time for this trip. What is the minimum total time to carry all numbers from one bank to another?




  • A man is running across a bridge.When he is 3/8 of the way accross, he heard a train coming behind him. If he keeps running he will reach the end of the bridge at the same time with the train. If he turns around and runs back, he will get to the beginning of the bridge at the same time with the train. The man runs at a speed of 5mph. What is the speed of the train?
    This was sent by John Sonmez from Texas.The interviewer asked him not to use paper but do the calculation in his head.
     




  • We are going to play a paper-rock game (similar to paper-rock-scissors). If we both have "paper" - I pay you $3, if we both have "rock" - I pay you $1. If they don't match - you pay me $2. Suggest a winning strategy?
     




  • There is a large cube that is composed of small sugar cubes. The large cube is 10 sugar cubes long, by 10 sugar cubes wide, by 10 sugar cubes high. How many sugar cubes are on the surface of the large cube?
    Received from Zach, college student





     
  • An escalator is descending at constant speed. A walks down and takes 50 steps to reach the bottom. B runs down and takes 90 steps in the same time as A takes 10 steps. how many steps are visible when the escalator is not operating.




     





    • There are 3 switches in one room that control 3 electrical lamps located in the other room.You are allowed to spend 5 minutes in the room with switches,change their position as you want.Then you should go to the room with lamps and tell exactly what switch controls every lamp.You can't return to the room with switches.




    • There is a pot full of water. How to pour out half of it without using a meter?




    • A point is chosen at random from within a circular region.What is the probability that the point is closer to the center of the region than it is to the boundary of the region.



    • Why  are  manhole  covers  round ?
      Sent by John M., LTX corp.




    • If you ask electronics engineer " To be  or  not to be ?" , his answer will be "One!"   How come?




    • You are playing a game with your partner.The idea is to cover a round table with quaters. The one who puts the last coin - wins.Suggest a winning strategy.
      Sent by Ronni , Oren Semiconductor




    • There are 8 metal balls, one of them is lighter. How many times do you need to weight the balls to find the light one? Try to minimize that number.



    • How to cut a plain circular cake for 8 people with just three straight cuts of knife?
       



    • A man went down to the river with two jugs, one of three-liter capacity and one of five-liter capacity. Using just these , how did he bring back exactly four liters?
       



    • You drove to the next town with a speed of 60 miles/hour. On your way back the speed was 40 miles/hour. The distance is 120 miles. Calculate the average speed.




       
    • How many gas stations in San-Francisco?





       




    • Here is a quickie someone from LSI Logic asked me a while back
      You are sitting in a boat in the middle of a lake. You pick up a rock from the boat and throw it into the lake. Did your action raise or lower the water level at the edge of the lake?





       




    • Why do they make pizza boxes square?
       




    • The bridge had 3 lanes. After reconstruction it will have 4 lanes. What is the persantage of the increase in carrying capacity?
       




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Electronics Hardware Questions

  • Two capacitors are connected in parallel through a switch. C1= 1uF, C2= 0.25uF.
    Initially the switch is open, C1 is charged to 10V. What happens if we close the switch? No losses in wires and capacitors. 

    Answers & follow ups
  • You have 2 switches to control the light in the long corridor. You want to be able to turn the light on entering the corridor and turn it off at the other end. Do the wiring circuit.
    Answers & follow ups
  • There are 3 switches that can turn on and off a light in the room. How to connect them?
    Answers & follow ups
  • What will be the voltage level between the 2 capacitors? The Vcc = 10v DC.
    Sent by Tanh, VLSI engineer

    Answers & follow ups
  • Suppose, you work on a specification for a system with some digital parameters. The spec table has has Min,Typ and Max colomns for each parameter. In what column would you put a Setup time and a Hold time?
    Answers & follow ups
  •   Design a simple circuit based on combinational logic to double the output frequency. 

    Answers & follow ups
  • 8bit ADC with parallel output converts an input signal into digital numbers. You have to come up with an idea of a circuit , that finds MAX  of every 10 numbers at the output of the ADC.
    Answers & follow ups
  • Implement a comparator that compares two 2-bit numbers A and B. The comparator should have 3 outputs:  A > B, A < B, A = B. Do it two ways:
    - using combinational logic;
    - using multiplexers. Write HDL code for your schematic at RTL and gate level.

    Answers & follow ups
  • You have a 8 bit ADC clocking data out every  1mS.  Design a system that  will sort the output data and keep the statistics of how often each binary number appears at the output of ADC.
     
    Answers & follow ups
  • What types of flip-flops do you know? 
     
    Answers & follow ups
  • Implement D- latch from
    - RS flip flop;
    - multiplexer.
    Answers & follow ups
  • How to convert D-latch into JK-latch and JK-latch into D-latch? 
    Answers & follow ups
  • There are two counters to 16, built from negedge D- FF . The first circuit is synchronous and the second one is "ripple" (cascading). Which circuit has less propagation delay?
    Answers & follow ups
  • What is the difference between a flip-flop and a latch? 
    Write an HDL code for their behavioral models.
    Hint from Hitequest
  • Describe the operation of a DAC. What are the most important parameters of a DAC? Do we really need both INL and DNL to estimate linearity? 
    Hint from Hitequest

     
  • Compare  briefly all types of ADC that you know .
    Hint from Hitequest
  • How will the output signal of an ideal integrator look like after
    - a positive pulse is applied to the input;
    - a series of 10 positive pulses ?
    Hint from Hitequest
  • How to design a divide-by-3 counter with equal duty cycle ?
    question from Anonymous
    Answers & follow ups
  • For an 8-bit flash A/D converter with an input range from 0V to 2.55V, describe what happens when the input voltage changes from 1.27V to 1.28V
    Answers & follow ups
  • Your system has CPU, ALU and two 8bit registers. There is no external memory. Can you swap the contence of the registers ?
    Answers & follow ups
  • We swapped 2 transistors in CMOS inverter (put n-transistor at the top and p-transistor at the bottom). Can this circuit work as a non-inverting buffer?
    (By E.Martovetsky,design eng)

    NO, IT CAN NOT! - Discussion with Sriram
    YES, IT CAN! - Discussion with Peter
    Yuri M., National Semi, PHD
  • Convert D-latch into divider by 2. 
    What is the max clock frequency  the circuit can handle ? 
    T_setup= 6nS 
    T_hold = 2nS 
    T_propagation = 10nS 
    Hint from Hitequest
  • The circle can rotate clockwise and back. Use minimum hardware to build a circuit to indicate the direction of rotating.

    Hint from Hitequest

     

  • Provide 2-dimentional plot of how the output of digital circuit will look like, if on axis X we sweep the clock period, while on axis Y we sweep the data setup time (Tclk vs Tsetup).

     
  • For chip design/test/product engineers :
    An IC device draws higher current when temperature gets:
    - higher?
    - lower?
    Hint from Hitequest

     
  • To enter the office people have to pass through the corridor. Once someone gets into the office the light turns on. It goes off when noone is present in the room. There are two registration sensors in the corridor.  Build a state machine diagram and design a circuit to control the light.


  • A voltage source with internal impedance Z_source = 50 OHm is connected to a transmission line with Z = 50 OHm. Z_load is also 50 OHm.
    The voltage source generates a single voltage step 1V.
    What will be the voltage level on the load:
     
    a)  2V , because the reflected signal will be in-phase with the incident signal;
    b)  0.33V , because the voltage is devided between Z_source , Z_load and Z_transm.line;
    c)  0.5V , because the voltage is devided between Z_source and Z_load.

    Hint from Hitequest

     
  • Draw a transistor schematic of NOR gate,it's layout and a cross section of the layout.
    This question is quite popular on interviews.


     
  • The silicon of a new device has memory leak. When all "0" are written into RAM, it reads back all "0" whithout any problem. When all "1" are written, only 80% of memory cells are read back correctly. What can be possibly the problem with the RAM?
    M.Altshuler, product engineer.


     
  • Draw a CMOS inverter. Why does CMOS technology dominate in VLSI manufacturing?
    L.Backer, DFT engineer


     
  • Design a FIFO 1 byte wide and 13 words deep. The FIFO is interfacing 2 blocks with different clocks. On the rising edge of clk the FIFO stores data and increments wptr. On the rising edge of clkb the data is put on the b-output,the rptr points to the next data to be read.
    If the FIFO is empty, the b-output data is not valid. When the FIFO is full the existing data should not be overriden.
    When rst_N is asserted, the FIFO pointers are asynchronously reset. module fifo1 (full,empty,clk,clkb,ain,bout,rst_N)
    output [7:0] bout;
    input [7:0] ain;
    input clk,clkb,rst_N;
    output empty, full;
    reg [3:0] wptr, rptr;
    ...
    endmodule

    Hint from Hitequest

     
  • What does CMOS stand for? VLSI? ASIC?
    This was in the series of quick questions in the interview at Analog Devices. We use these abbreviations daily, but not everyone remembers what they stand for.
    Hint from Hitequest




     
  • Design a COMBINATIONAL circuit that can divide the clock frequency by 2.


     
  • Design a 2bit up/down counter with clear using gates. (No verilog or vhdl)


     
  • We have a circular wheel with half painted black and the other half painted white. There are 2 censors mounted 45 degree apart at the surface of this wheel( not touching the wheel) which give a "1" for black and "0" for white passing under them. Design a circuit to detect which way the wheel is moving. Can not assume any fixed position for start.


     
  • We have a FIFO which clocks data in at 100mhz and clocks data out at 80mhz. On the input there are only 80 data bits in any order during each 100 clocks. In other words, a 100 input clock will carry only 80 data bits, and the other twenty clocks carry no data (data is scattered in any order). How big the FIFO needs to be to avoid data over/under-run.
    Follow Ups




     
  • Instead of specifying SETUP and HOLD time, can we just specify a SETUP time for '1' and a SETUP time for '0'?
    Follow ups




     
  • Here some hardware digital design specific questions, offered by Suhas:
    (1) When will you use a latch and a flipflop in a sequential design?
    (2) Design a 1-bit fulladder using a decoder and 2 "or" gates?
    (3) You have a circuit operating at 20 MHz and 5 volt supply. What would you do to reduce the power consumption in the circuit- reduce the operating frequency of 20Mhz or reduce the power supply of 5Volts and why?
    (4) In a nmos transistor, how does the current flows from drain to source in saturation region when the channel is pinched off?
    (5) In a SRAM circuit, how do you design the precharge and how do you size it?
    (6) In a PLL, what elements(like XOR gates or Flipflops) can be used to design the phase detector?
    (7) While synthesis of a design using synopsys design compiler, why do you specify input and output delays?
    (8) What difference do you see in the timing reports for a propogated clock and an ideal clock?
    (9) What is timeborrowing related to Static timing anaylsis in Primetime?

     
  • What is the purpose of a diode next to relay on schematics?

    Answers & follow ups
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Digital design interview questions & answers.





1) Explain about setup time and hold time, what will happen if there is setup time and hold tine violation, how to overcome this?
Set up time is the amount of time before the clock edge that the input signal needs to be stable to guarantee it is accepted properly on the clock edge.
Hold time is the amount of time after the clock edge that same input signal has to be held before changing it to make sure it is sensed properly at the clock edge.
Whenever there are setup and hold time violations in any flip-flop, it enters a state where its output is unpredictable: this state is known as metastable state (quasi stable state); at the end of metastable state, the flip-flop settles down to either '1' or '0'. This whole process is known as metastability

2) What is skew, what are problems associated with it and how to minimize it? 
In circuit design, clock skew is a phenomenon in synchronous circuits in which the clock signal (sent from the clock circuit) arrives at different components at different times.
This is typically due to two causes. The first is a material flaw, which causes a signal to travel faster or slower than expected. The second is distance: if the signal has to travel the entire length of a circuit, it will likely (depending on the circuit's size) arrive at different parts of the circuit at different times. Clock skew can cause harm in two ways. Suppose that a logic path travels through combinational logic from a source flip-flop to a destination flip-flop. If the destination flip-flop receives the clock tick later than the source flip-flop, and if the logic path delay is short enough, then the data signal might arrive at the destination flip-flop before the clock tick, destroying there the previous data that should have been clocked through. This is called a hold violation because the previous data is not held long enough at the destination flip-flop to be properly clocked through. If the destination flip-flop receives the clock tick earlier than the source flip-flop, then the data signal has that much less time to reach the destination flip-flop before the next clock tick. If it fails to do so, a setup violation occurs, so-called because the new data was not set up and stable before the next clock tick arrived. A hold violation is more serious than a setup violation because it cannot be fixed by increasing the clock period.
Clock skew, if done right, can also benefit a circuit. It can be intentionally introduced to decrease the clock period at which the circuit will operate correctly, and/or to increase the setup or hold safety margins. The optimal set of clock delays is determined by a linear program, in which a setup and a hold constraint appears for each logic path. In this linear program, zero clock skew is merely a feasible point.
Clock skew can be minimized by proper routing of clock signal (clock distribution tree) or putting variable delay buffer so that all clock inputs arrive at the same time

3) What is slack?

'Slack' is the amount of time you have that is measured from when an event 'actually happens' and when it 'must happen’.. The term 'actually happens' can also be taken as being a predicted time for when the event will 'actually happen'.
When something 'must happen' can also be called a 'deadline' so another definition of slack would be the time from when something 'actually happens' (call this Tact) until the deadline (call this Tdead).
Slack = Tdead - Tact.
Negative slack implies that the 'actually happen' time is later than the 'deadline' time...in other words it's too late and a timing violation....you have a timing problem that needs some attention.

4) What is glitch? What causes it (explain with waveform)? How to overcome it?



The following figure shows a synchronous alternative to the gated clock using a data path. The flip-flop is clocked at every clock cycle and the data path is controlled by an enable. When the enable is Low, the multiplexer feeds the output of the register back on itself. When the enable is High, new data is fed to the flip-flop and the register changes its state



5) Given only two xor gates one must function as buffer and another as inverter?

Tie one of xor gates input to 1 it will act as inverter.
Tie one of xor gates input to 0 it will act as buffer.

6) What is difference between latch and flipflop?

The main difference between latch and FF is that latches are level sensitive while FF are edge sensitive. They both require the use of clock signal and are used in sequential logic. For a latch, the output tracks the input when the clock signal is high, so as long as the clock is logic 1, the output can change if the input also changes. FF on the other hand, will store the input only when there is a rising/falling edge of the clock.

7) Build a 4:1 mux using only 2:1 mux?



Difference between heap and stack?

The Stack is more or less responsible for keeping track of what's executing in our code (or what's been "called"). The Heap is more or less responsible for keeping track of our objects (our data, well... most of it - we'll get to that later.).
Think of the Stack as a series of boxes stacked one on top of the next. We keep track of what's going on in our application by stacking another box on top every time we call a method (called a Frame). We can only use what's in the top box on the stack. When we're done with the top box (the method is done executing) we throw it away and proceed to use the stuff in the previous box on the top of the stack. The Heap is similar except that its purpose is to hold information (not keep track of execution most of the time) so anything in our Heap can be accessed at any time. With the Heap, there are no constraints as to what can be accessed like in the stack. The Heap is like the heap of clean laundry on our bed that we have not taken the time to put away yet - we can grab what we need quickly. The Stack is like the stack of shoe boxes in the closet where we have to take off the top one to get to the one underneath it.

9) Difference between mealy and moore state machine?

A) Mealy and Moore models are the basic models of state machines. A state machine which uses only Entry Actions, so that its output depends on the state, is called a Moore model. A state machine which uses only Input Actions, so that the output depends on the state and also on inputs, is called a Mealy model. The models selected will influence a design but there are no general indications as to which model is better. Choice of a model depends on the application, execution means (for instance, hardware systems are usually best realized as Moore models) and personal preferences of a designer or programmer

B) Mealy machine has outputs that depend on the state and input (thus, the FSM has the output written on edges)
Moore machine has outputs that depend on state only (thus, the FSM has the output written in the state itself.

Adv and Disadv
In Mealy as the output variable is a function both input and state, changes of state of the state variables will be delayed with respect to changes of signal level in the input variables, there are possibilities of glitches appearing in the output variables. Moore overcomes glitches as output dependent on only states and not the input signal level.
All of the concepts can be applied to Moore-model state machines because any Moore state machine can be implemented as a Mealy state machine, although the converse is not true.
Moore machine: the outputs are properties of states themselves... which means that you get the output after the machine reaches a particular state, or to get some output your machine has to be taken to a state which provides you the output.The outputs are held until you go to some other state Mealy machine:
Mealy machines give you outputs instantly, that is immediately upon receiving input, but the output is not held after that clock cycle.

10) Difference between onehot and binary encoding?

Common classifications used to describe the state encoding of an FSM are Binary (or highly encoded) and One hot.
A binary-encoded FSM design only requires as many flip-flops as are needed to uniquely encode the number of states in the state machine. The actual number of flip-flops required is equal to the ceiling of the log-base-2 of the number of states in the FSM.
A onehot FSM design requires a flip-flop for each state in the design and only one flip-flop (the flip-flop representing the current or "hot" state) is set at a time in a one hot FSM design. For a state machine with 9- 16 states, a binary FSM only requires 4 flip-flops while a onehot FSM requires a flip-flop for each state in the design
FPGA vendors frequently recommend using a onehot state encoding style because flip-flops are plentiful in an FPGA and the combinational logic required to implement a onehot FSM design is typically smaller than most binary encoding styles. Since FPGA performance is typically related to the combinational logic size of the FPGA design, onehot FSMs typically run faster than a binary encoded FSM with larger combinational logic blocks

11) What are different ways to synchronize between two clock domains?

12) How to calculate maximum operating frequency?

13) How to find out longest path?

You can find answer to this in timing.ppt of presentations section on this site

14) Draw the state diagram to output a "1" for one cycle if the sequence "0110" shows up (the leading 0s cannot be used in more than one sequence)?


15) How to achieve 180 degree exact phase shift?


Never tell using inverter
a) dcm’s an inbuilt resource in most of fpga can be configured to get 180 degree phase shift.
b) Bufgds that is differential signaling buffers which are also inbuilt resource of most of FPGA can be used.

16) What is significance of ras and cas in SDRAM?

SDRAM receives its address command in two address words.
It uses a multiplex scheme to save input pins. The first address word is latched into the DRAM chip with the row address strobe (RAS).
Following the RAS command is the column address strobe (CAS) for latching the second address word.
Shortly after the RAS and CAS strobes, the stored data is valid for reading.

17) Tell some of applications of buffer?

a)They are used to introduce small delays
b)They are used to eliminate cross talk caused due to inter electrode capacitance due to close routing.
c)They are used to support high fanout,eg:bufg


18) Implement an AND gate using mux?

This is the basic question that many interviewers ask. for and gate, give one input as select line,incase if u r giving b as select line, connect one input to logic '0' and other input to a.

19) What will happen if contents of register are shifter left, right?

It is well known that in left shift all bits will be shifted left and LSB will be appended with 0 and in right shift all bits will be shifted right and MSB will be appended with 0 this is a straightforward answer

What is expected is in a left shift value gets Multiplied by 2 eg:consider 0000_1110=14 a left shift will make it 0001_110=28, it the same fashion right shift will Divide the value by 2.

20)Given the following FIFO and rules, how deep does the FIFO need to be to prevent underflow or overflow?

RULES:
1) frequency(clk_A) = frequency(clk_B) / 4
2) period(en_B) = period(clk_A) * 100
3) duty_cycle(en_B) = 25%


Assume clk_B = 100MHz (10ns)
From (1), clk_A = 25MHz (40ns)
From (2), period(en_B) = 40ns * 400 = 4000ns, but we only output for
1000ns,due to (3), so 3000ns of the enable we are doing no output work. Therefore, FIFO size = 3000ns/40ns = 75 entries.
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